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SMB113A/B/SMB117/A
High-power, Four-channel Programmable DC-DC System Power Managers
FEATURES & APPLICATIONS
* Digital programming of all major parameters via I2C interface and non-volatile memory * Output voltage set point * Input/battery voltage monitoring * Output power-up/down sequencing * Digital soft-start and output slew rate * Dynamic voltage control of all outputs * UV/OV monitoring of all outputs * Enable/Disable outputs independently * User friendly Graphical User Interface (GUI) * Four synchronous step-down output channels * Integrated RESET monitor * +2.7V to +6.0V Input Range * Highly accurate output voltage: <1.5% * Factory programmable dead times * 0% to 100% Duty Cycle operation * Undervoltage Lockout (UVLO) with hysteresis * 250kHz (SMB117A), 400kHz (SMB117), 800kHz (SMB113A), 1MHz (SMB113B) operating frequency * 96 bytes of user configurable nonvolatile memory Preliminary Information
INTRODUCTION
The SMB113A/B and SMB117/A are highly integrated and flexible four-channel power managers designed for use in a wide range of applications. The built-in digital programmability allows system designers to custom tailor the device to suit almost any multi-channel power supply application from digital camcorders to set-top boxes. Complete with a user friendly GUI, all programmable settings, including output voltages and input/output voltage monitoring, can be customized with ease. The SMB113A/B and SMB117/A integrate all the essential blocks required to implement a complete four-channel power subsystem consisting of four synchronous step-down "buck" controllers. Additionally sophisticated power control/monitoring functions required by complex systems are built-in. These include digitally programmable output voltage set point, powerup/down sequencing, enable/disable, dynamic voltage management and UV/OV monitoring on all channels. The integration of features and built-in flexibility of the SMB113A/B and SMB117/A allows the system designer to create a "platform solution" that can be easily modified via software without major hardware changes. Combined with the re-programmability of the SMB113A/B and SMB117/A, this facilitates rapid design cycles and proliferation from a base design to future product generations. The SMB113A/B and SMB117/A are suited to a wide variety of applications with an input range of +2.7V to +6.0V. Higher input voltage operation can easily be implemented with a small number of external components. Output voltages are extremely accurate (<1.5%). Communication is accomplished 2 via the industry standard I C bus. All user-programmed settings are stored in non-volatile EEPROM of which 96 bytes may be used as general-purpose memory. The devices are offered in both the commercial and the industrial operating temperature range. The package type is a lead-free, RoHS compliant, 5x5 QFN-32.
Applications
* * * * * * Car & Marine Navigation Systems Set-top Boxes TVs DDR Memory Mobile Computing/PDAs Office Equipment * DMB Systems
SIMPLIFIED APPLICATIONS DRAWING
+2.7V to +6.0V or Li-Ion
SMB113A/B
+0.5V to Vin (Prog.) @ 1.5A/5A
+2.7V to +6.0V or Li-Ion CPU Core I2C/SMBus
SMB117/A
+0.5V to Vin (Prog.) @ 5A/10A
CPU Core
I2C/SMBus
Enable Input Reset Input
System Control and Monitoring
4 StepDown (Buck) Channels
+0.5V to Vin (Prog.) @ 1.5A/5A
Memory, I/O
Enable Input Reset Input
System Control and Monitoring
+0.5V to Vin (Prog.) @ 1.5A/5A
DSP/Codec
4 StepDown (Buck) Channels
+0.5V to Vin (Prog.) @ 5A/10A
Memory, I/O
+0.5V to Vin (Prog.) @ 5A/10A
DSP/Codec
RESET Output (Power Good)
RESET Monitor
+0.5V to Vin (Prog.) @ 1.5A/5A
Analog/RF
RESET Output (Power Good)
RESET Monitor
+0.5V to Vin (Prog.) @ 5A/10A
Analog/RF
Figure 1 - Applications schematic featuring the SMB113A/B/117/A programmable DC-DC controllers. Note: This is an applications example only. Some pins, components and values are not shown.
(c) SUMMIT Microelectronics, Inc. 2007
757 N. Mary Avenue * Sunnyvale CA 94085 Phone 408 523-1000 * FAX 408 523-1266
http://www.summitmicro.com/
2111 2.4 6/24/2008
1
SMB113A/B/SMB117/A
Preliminary Information
GENERAL DESCRIPTION
The SMB113A/B and SMB117/A are fully programmable DC-DC controllers that incorporate power delivery and advanced power monitoring and control functionality. The devices integrate four synchronous "buck" stepdown controllers in a space saving package. The SMB113A uses a fixed 800kHz whereas the SMB113B uses a fixed 1MHz, the SMB117 a fixed 400kHz and the SMB117A a fixed 250kHz Pulse Width Modulation (PWM) control circuit. A type-three voltage mode compensation network is used offering a cost effective solution without compromising transient response performance. By utilizing external N- and P- type MOSFET transistors the efficiency and load current level can be customized to fit a wide array of system requirements. The SMB113A/B and SMB117/A contain four buck outputs capable of producing an output voltage less than the input voltage. Each buck output voltage is set by an internal resistor divider and a programmable voltage reference. The integrated resistor divider eliminates the cost and space necessary for external components and has several programmable values. Through the programmability of the reference and the resistor divider, practically any output voltage smaller than the battery can be produced without the need to change external components. The SMB113A/B and SMB117/A are capable of poweron/off cascade sequencing where each channel can be assigned one of four unique sequence positions. During sequencing each channel in a given sequencing position is guaranteed to reach its programmed output voltage before the channel(s) occupying the next sequence position initiate their respective soft-start sequence. A unique programmable delay exists between each power on/off sequence position. In addition to power on/off sequencing all supplies can be powered on/off individually through an I2C command or by assertion of the enable pin. Each output voltage is monitored for under-voltage and over-voltage (UV/OV) conditions, using a comparatorbased circuit where the output voltage is compared against an internal programmable reference. An additional feature of the output voltage monitoring is a programmable glitch filter capable of digitally filtering a transient OV/UV fault condition from a true system error. When a fault is detected for a period in excess of the glitch filter, all supplies may be sequenced down or immediately disabled and an output status pin can be asserted. The current system status is always accessible via internal registers containing the status of all four channels. The SMB113A/B and SMB117/A also possess an Under-voltage Lockout (UVLO) circuit to ensure the devices will not power up until the input voltage has reached a safe operating voltage. The UVLO function exhibits hysteresis, ensuring that noise or a brown out voltage on the supply rail does not inadvertently lead to a system failure. The SMB113A/B and SMB117/A provide dynamic voltage management over all of their output voltages. Through an I2C command, all output voltage levels can be increased or decreased to a pre-programmed level. In addition, each output is slew rate limited by soft-start circuitry that is user-programmable and requires no external capacitors. All programmable settings on the SMB113A/B and the SMB117/A are stored in non-volatile registers and are easily accessed and modified over an industry standard I2C serial bus. For fastest prototype development times Summit offers an evaluation card and a Graphical User Interface (GUI).
Summit Microelectronics, Inc.
2111 2.4 6/24/2008
2
SMB113A/B/SMB117/A
Preliminary Information
TYPICAL APPLICATION
VIN: +2.7V to +6.0V
SMB113A/B (SMB117/A)
VBATT VDDCAP GND HSDRV_CH3 +0.8V to VIN @ 5A (10A) HVSUP3
LSDRV_CH3
SDA SCL PWREN
VM_CH3 COMP1_CH3 COMP2_CH3
HEALTHY/nRESET HOST_RESET HVSUP2
HSDRV_CH2 HVSUP0 HSDRV_CH0 +0.8V to VIN @ 5A (10A) LSDRV_CH2 +0.8V to VIN @ 5A (10A)
LSDRV_CH0
VM_CH2 COMP1_CH2
VM_CH0 COMP1_CH0
COMP2_CH2 HVSUP1
COMP2_CH0 HSDRV_CH1 +0.8V to VIN @ 5A (10A)
LSDRV_CH1
VM_CH1 COMP1_CH1 COMP2_CH1
Figure 2 - Typical application schematic
Summit Microelectronics, Inc
2111 2.4 6/24/2008
3
SMB113A/B/SMB117/A
Preliminary Information
INTERNAL BLOCK DIAGRAM
COMP2_CH[0,1,2,3] VM_CH[0,1,2,3]
100k - + OA + - CLAMP MAX LIMIT LOW LIMIT DUTY CYCLE LIMIT OSC
Fixed 250/400/ 800/1000kHz
HVSUP[0,1,2,3]
Channel 0,1,2,3 Synchronous buck PWM Converter
HSDRV[0,1,2,3]
I2C/SMBUS SDA SCL COMP1_CH[0,1,2,3]
VREF LEVEL SHIFTER DIGITAL TO ANALOG CONVERTER
DEADTIME
+ -
GLITCH FILTER
OVER VOLTAGE DETECTION
LSDRV[0,1,2,3]
SEQUENCING AND MONITORING LOGIC ENABLE
PWREN0
+ - VREF VREF
GLITCH FILTER
UNDER VOLTAGE DETECTION
VBATT
VDDCAP
GND
BANDGAP
VDD_CAP
2.5V REGULATOR
+ -
UV2
D Q
LEVEL SHIFTER VREF
+ -
UV1
Figure 3 -SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
4
SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number Pin Type Pin Name Pin Description The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper switching node of the channel 0 synchronous step-down buck controller. Attach to the gate of p-channel MOSFET. A delay exists between the assertion of HSDRV_CH0 and assertion of LSDRV_CH0 to prevent excessive current flow during switching. The HEALTHY pin is an open drain output. High when all enabled output supplies are within the programmed levels. HEALTHY will ignore any disabled supply. There is a programmable glitch filter on the under-voltage and over-voltage sensors so that short transients outside of the limits will be ignored by HEALTHY. This pin can also be programmed to act as a Reset Output (nRESET). In this case, it releases with a programmable delay after all outputs are valid. When used, this pin should be pulled high by an external pull-up resistor. The COMP1_CH0 (Channel 0 primary Compensation) pin is the primary feedback input of the channel 0 step-down buck controller. The COMP1_CH0 pin is internally connected to a programmable resistor divider. The COMP2_CH0 (Channel 0 secondary Compensation) pin is the secondary feedback input of the channel 0 step-down buck controller. The VM_CH0 (Channel 0 Voltage Monitor) pin connects the channel 0 step-down controller output. Internally the VM_CH0 pin connects to a programmable resistor divider. SDA (Serial Data) is an open drain bi-directional pin used as the I2C data line. SDA must be tied high through a pull-up resistor. SCL (Serial Clock) is an open drain input pin used as the I2C clock line. SCL must be tied high through a pull-up resistor. The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower switching node of the channel 1 synchronous step-down buck controller. Attach to the gate of n-channel MOSFET. Channel 1 High Voltage Supply for Channel 1 buck driver. The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper switching node of the channel 1 synchronous step-down buck controller. Attach to the gate of p-channel MOSFET. A delay exists between the assertion of HSDRV_CH1 and assertion of LSDRV_CH1 to prevent excessive current flow during switching. The HOST_RESET pin is an active high reset input. When this pin is asserted high, the nRESET output will immediately go low. When HOST_RESET is brought low, nRESET will go high after a programmed reset delay. When pin 2 is used as a HEALTHY output, this pin needs to be attached to GND or VBATT via a resistor. The COMP1_CH1 (Channel 1 primary Compensation) pin is the primary compensation input of the channel 1 step-down buck controller. The COMP1_CH1 pin is internally connected to a programmable resistor divider. The COMP2_CH1 (Channel 1 secondary Compensation) pin is the secondary compensation input of the channel 1 step-down buck controller.
2111 2.4 6/24/2008
1
OUT
HSDRV_CH0
2
OUT
HEALTHY (nRESET)
3
IN
COMP1_CH0
4 5 6 7 8 9
IN IN I/O IN OUT PWR
COMP2_CH0 VM_CH0 SDA SCL LSDRV_CH1 HVSUP1
10
OUT
HSDRV_CH1
11
IN
HOST_RESET
12
IN
COMP1_CH1
13
IN
COMP2_CH1
Summit Microelectronics, Inc
5
SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number 14 15 16 17 18 Pin Type IN CAP PWR OUT PWR Pin Name VM_CH1 VDD_CAP VBATT LSDRV_CH2 HVSUP2 Pin Description The VM_CH1 (Channel 1 Voltage Monitor) pin connects the channel 1 step-down controller output. Internally the VM_CH1 pin connects to an internal programmable resistor divider. The VDD_CAP (VDD Capacitor) pin is an external capacitor input used to filter the internal supply. Power supply to part. The LSDRV_CH2 (Channel 2 Low-side Driver) pin is the lower switching node of the channel 2 synchronous step-down buck controller. Attaches to the gate of n-channel MOSFET. Channel 2 High Voltage Supply for Channel 2 buck driver. The HSDRV_CH2 (Channel 2 High-side Driver) pin is the upper switching node of the channel 2 synchronous step-down buck controller. Attach to the gate of p-channel MOSFET. A delay exists between the assertion of HSDRV_CH2 and assertion of LSDRV_CH2 to prevent excessive current flow during switching. The COMP2_CH2 (Channel 2 secondary Compensation) pin is the secondary compensation input of the channel 2 step-down buck controller. The COMP1_CH2 (Channel 2 primary Compensation) pin is the primary compensation input of the channel 2 step-down buck controller. Each pin is internally connected to a programmable resistor divider. The VM_CH2 (Channel 2 Voltage Monitor) pin connects the channel 6 step-down controller output. Internally the VM_CH2 pin connects to an internal programmable resistor divider. The LSDRV_CH3 (Channel 3 Low-side Driver) pin is the lower switching node of the channel 3 synchronous step-down buck controller. Attaches to the gate of n-channel MOSFET. Channel 3 High Voltage Supply for Channel 3 buck driver. The HSDRV_CH3 (Channel 3 High-side Driver) pin is the upper switching node of the channel 3 synchronous step-down buck controller. Attach to the gate of p-channel MOSFET. A delay exists between the assertion of HSDRV_CH3 and assertion of LSDRV_CH3 to prevent excessive current flow during switching. The PWREN (Power Enable) pin is a programmable input used to enable (disable) selected supplies. This pin can also be programmed to latch and act as a debounced, manual push button input. Active high when level triggered, active low when used as a push- button input. When unused this pin should be tied to a solid logic level. The COMP2_CH3 (Channel 3 secondary Compensation) pin is the secondary compensation input of the channel 3 step-down buck controller. The COMP1_CH3 (Channel 3 primary Compensation) pin is the primary compensation input of the channel 3 step-down buck controller. Each pin is internally connected to a programmable resistor divider.
19
OUT
HSDRV_CH2
20
IN
COMP2_CH2
21
IN
COMP1_CH2
22
IN
VM_CH2
23 24
OUT PWR
LSDRV_CH3 HVSUP3
25
OUT
HSDRV_CH3
26
IN
PWREN
27
IN
COMP2_CH3
28
IN
COMP1_CH3
Summit Microelectronics, Inc
2111 2.4 6/24/2008
6
SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number 29 30 31 32 PAD Pin Type IN PWR OUT PWR PWR Pin Name VM_CH3 GND LSDRV_CH0 HVSUP0 GND Pin Description The VM_CH3 (Channel 3 Voltage Monitor) pin connects the channel 3 step-down controller output. Internally the VM_CH3 pin connects to an internal programmable resistor divider. Ground The LSDRV_CH0 (Channel 0 Low-side Driver) pin is the lower switching node of the channel 0 synchronous step-down buck controller. Attach to the gate of n-channel MOSFET. Channel 0 High Voltage Supply used to power the channel 0 buck driver. Exposed metal (thermal) Pad on bottom of SMB113A/B and SMB117/A. The thermal pad of the QFN package must be connected to the PCB GND.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
7
SMB113A/B/SMB117/A
Preliminary Information
PACKAGE AND PIN DESCRIPTION
Top View
SMB113A/B/SMB117/A 5mm x 5mm QFN-32
COMP1_CH3 COMP2_CH3 HSDRV_CH3 LSDRV_CH0 VM_CH3 HVSUP0
32
31
30
29
28
27
26
PWREN
GND
25
HSDRV_CH0 HEALTHY (nRESET) COMP1_CH0 COMP2_CH0 VM_CH0 SDA SCL LSDRV_CH1
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
HVSUP3 LSDRV_CH3 VM_CH2 COMP1_CH2 COMP2_CH2 HSDRV_CH2 HVSUP2 LSDRV_CH2
GND
9
HVSUP1
10
HSDRV_CH1
11
HOST_RESET
12
COMP1_CH1
13
COMP2_CH1
14
VM_CH1
15
VDD_CAP
16
VBATT
Summit Microelectronics, Inc
2111 2.4 6/24/2008
8
SMB113A/B/SMB117/A
Preliminary Information ABSOLUTE MAXIMUM RATINGS Temperature Under Bias .................... -55C to +125C Storage Temperature.......................... -65C to +150C Terminal Voltage with Respect to GND: VBATT Supply Voltage ................... -0.3V to +6.5V HVSUP Supply Voltage .................. -0.3V to +6.5V All Others ...................................... -0.3V to VBATT Output Short Circuit Current .............................100mA Reflow Solder Temperature (30 secs)............... +260C Junction Temperature........................................ +150C ESD Rating per JEDEC ..................................... +2000V Latch-Up testing per JEDEC............................. 100mA RECOMMENDED OPERATING CONDITIONS Commercial Temperature Range............... 0C to +70C Industrial Temperature Range ................ -40C to +85C VBATT Supply Voltage ........................... +2.7V to +6.0V HVSUP Supply Voltage........................... +2.7V to +6.0V All Others.................................................GND to VBATT Package Thermal Resistance (JA), 32-Lead QFN (thermal pad connected to PCB)....................... 37.2C/W Moisture Classification Level 3 (MSL 3) per J-STD-020 RELIABILITY CHARACTERISTICS Data Retention ................................................ 100 Years Endurance ................................................ 100,000 Cycle Temperature Range ................................ -40C to +85C
Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max VBATT VHVSUP VUVLO IDD-MONITOR IDD-ACTIVE VDD_CAP Oscillator SMB113B fOSC Oscillator frequency SMB113A SMB117 SMB117A OPP LT fSV fST Oscillator peak-to-peak Frequency stability for voltage Frequency stability for temperature +25C to +70C, fOSC = 800kHz +25C to +85C, fOSC = 800kHz 875 720 360 212 1000 800 400 250 1 0.1 0.18 0.22 1125 880 440 288 V %/V kHz/ C kHz Input supply voltage Buck driver supply voltage Under-voltage lockout Monitoring current Active current Internal supply, present on VDD_CAP pin Input supply voltage (operational) Gate drive voltage VBATT rising VBATT falling All voltage inputs monitored. No supplies switching, VBATT at 4.2V. Total current all channels enabled. No load. VBATT at 4.2V. Note 2. No load 2.4 1.9 2.7 2.7 2.2 2.0 290 1.2 2.5 400 2.0 2.6 6.0 6.0 2.3 Unit V V V V A mA V
Summit Microelectronics, Inc
2111 2.4 6/24/2008
9
SMB113A/B/SMB117/A
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Min Typ Max Error Amplifier AVOL BW ISOURCE ISINK Open loop voltage Gain Frequency bandwidth Output source current Output sink current At DC At AVOL = 0 dB At 0.5V At 0.5V 60 30 20 800 Unit dB MHz A A
Output Block VOUT Voltage set point range. 100% Maximum Duty cycle Output accuracy, excluding external resistor divider1 HSDRV ON resistance VBATT= 4.2V, ILOAD=0 VOUT = VBATT x (duty cycle) VBATT= 6.0V, ILOAD=0 VOUT = VBATT x (duty cycle) Commercial temperature range Industrial temperature range Output high Output low Output high Output low COMP1 pin Programmable in 4mV steps High Duty Cycle Low Duty Cycle, Note 3 High Duty Cycle, Note 3 Low Duty Cycle
0.7 x VDD_CAP
0.5 0.5 -1.5 -2.0 2 2 2 2 1.0 100
4.2 V 6.0 +1.5 +2.0 %
VOUT
RDRVH
RDRVL VCOMP1
LSDRV ON resistance Feedback voltage reference 100% Max Duty Cycle
V
D.C. 90% Max Duty Cycle Logic Levels VIH VIL VOL Input high voltage Input low Open drain outputs
35 70 0
%
6.0
0.3 x VDD_CAP
V V V
0 ISINK = 1mA 0
0.4
Summit Microelectronics, Inc
2111 2.4 6/24/2008
10
SMB113A/B/SMB117/A
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Symbol Parameter Conditions Programmable UV1 threshold voltage measured on VBATT pin in 150 mV increments Programmable UV2 threshold voltage measured on VBATT pin in 150 mV increments Min Typ Max Unit Programmable Monitoring Thresholds VPUV1 VPUV2 VPUV2 VPUV1 Programmable UV1 threshold Programmable UV2 threshold UV2 accuracy UV1 accuracy -3 PUVTH Programmable under-voltage threshold Output voltage relative to nominal operating voltage. Note 3. -8 -12 -16 +3 POVTH Programmable over-voltage threshold Output voltage relative to nominal operating voltage. Note 3. +8 +12 +16 2.55 2.55 2 2 -5 -10 -15 -20 +5 +10 +15 +20 -7 -12 -18 -24 +7 +12 +18 +24 % % 3.60 3.60 V V % %
Note 1: Voltage accuracies are only guaranteed for factory-programmed settings. Changing the output voltage from that reflected in the customer specific CSIR code might result in inaccuracies exceeding those specified above by 1%. Note 2: For more accurate active current levels under several load conditions, Summit's proprietary design software can be used. Contact the factory for more information. Note 3: Guaranteed by Design and Characterization - not 100% tested in Production.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
11
SMB113A/B/SMB117/A
Preliminary Information
AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Note 4 Symbol Description Conditions Min Typ Max Unit 1.5 12.5 Programmable power-On Programmable power-on sequence tPPTO ms sequence timeout period. position to sequence position delay. 25 50 1.5 12.5 Programmable power-off Programmable power-off sequence ms tDPOFF sequence timeout period. position to sequence position delay. 25 50 Time between active enable in which OFF corresponding outputs must exceed there 50 Programmable sequence programmed under voltage threshold. If ms tPST termination period 100 exceeded, a force shutdown will be 200 initiated. 0 Period for which fault must persist before Programmable glitch filter tPGF s fault triggered actions are taken. 8 25 Applicable when HEALTHY pin is used as 50 an nRESET output pin. Programmable Reset timeout period tRESET ms time following assertion of last supply 100 before nRESET pin is released high. 200 400 200 100 67 Programmable slew rate Adjustable slew rate factor proportional to SRREF V/s reference output slew rate. 50 33 25 20 Channels 0 to 3 tRL tFL tRL tFL tDT LS Driver output rise time LS Driver output fall time HS Driver output rise time HS Driver output fall time Driver non-overlap delay CG=100pF, VBATT=4.2V CG=100pF, VBATT=4.2V CG=100pF, VBATT=4.2V CG=100pF, VBATT=4.2V High to low transition on HSDRV Low to high transition on buck HSDRV 4.2 4.2 2.9 2.9 30 60 ns ns ns ns ns
Note 4: Timing specifications are 20% shorter for the SMB113B device and 60% longer for SMB117A.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
12
SMB113A/B/SMB117/A
Preliminary Information
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS - 100 kHz
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) 100kHz Symbol Description Conditions Min Typ Max Units fSCL TLOW THIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR_CONFIG tWR_EE SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to data valid Data output hold time SCL and SDA rise time SCL and SDA fall time Data in setup time Data in hold time Noise filter SCL and SDA Write cycle time config Write cycle time EE Noise suppression Configuration registers Memory array SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change Note 5 Note 5 250 0 136 10 5 Before new transmission - Note 5 0 4.7 4.0 4.7 4.7 4.0 4.7 0.2 0.2 1000 300 3.5 100 kHz s s s s s s s s ns ns ns ns ns ms ms
Note 5: Guaranteed by Design.
TIMING DIAGRAMS
tR SCL tSU:STA SDA (IN) tAA SDA (OUT)
tF tHD:STA
tHIGH tHD:DAT
tWR (For Write Operation Only) tLOW tSU:DAT tDH tSU:STO tBUF
Figure 4 - I2C timing diagram
Summit Microelectronics, Inc
2111 2.4 6/24/2008
13
SMB113A/B/SMB117/A
Preliminary Information
SMB113A EFFICIENCY GRAPHS
Efficiency at 3.3V
100 95
100 95
Efficiency at 2.5V
Efficiency (%)
90 85 80 75
Efficiency (%)
90 85 80 75 70 65 60 0 0.5 1 1.5
5.0V
70 65 60 0 0.5 1 1.5
4.2V 3.8V 3.6V 3.4V
2
5.0V 4.2V 3.8V 3.6V 3.3V 3.0V
2
Current (Amps)
100 95
Efficiency at 1.8V
C urrent (A ps) m
Efficiency (%)
90 85 80 75 70 65 60
5.0V 4.2V 3.8V 3.6V 3.3V 3.0V
0 0.5 1 1.5
100 95
Efficiency at 1.5V
100 95
2
C rren (A p u t m s)
Efficiency (%)
Efficiency at 1.2V
Efficiency (%)
90 85 80 75 70 65 60 0 0.5 1 1.5
90 85 80 75 70 65 60 0 0.5 1 1.5
5.0V 4.2V 3.8V 3.6V 3.3V 3.0V
2
5.0V 3.8V 4.2V 3.6V 3.3V 3.0V
2
C rren (A p u t m s)
Summit Microelectronics, Inc 2111 2.4 6/24/2008
Current (Amps)
14
SMB113A/B/SMB117/A
Preliminary Information
SMB117 EFFICIENCY GRAPHS
Efficiency at 1.2V, 1.8V, 2.5V, 3.3V
100 90 80
Efficiency (%)
70 60 50 40 30 20 10 0 0 2 4 Vin = 5.0 Volts 1.2V 1.8V 2.5V 3.3V
Current (Amps)
6
8
10
12
Buck 2.5V
Summit Microelectronics, Inc
2111 2.4 6/24/2008
15
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION DEVICE OPERATION
POWER SUPPLY There are five supply input pins on the SMB113A/B and SMB117/A: four HVSUP pins and the VBATT pin. Each supply must be powered from an input voltage between 2.7-6.0 volts. The HVSUP1 though HVSUP4 are used to power the HSDRV (PMOS driver) and LSDRV (NMOS driver) outputs. The rail-to-rail swing on the HSDRV and LSDRV pins is equal to the associated HVSUP supply voltage. The VBATT pin is internally regulated to 2.5V. This 2.5V supply is then filtered on the VDD_CAP pin and used to power all internal circuitry. The VBATT pin is monitored by an Under-Voltage Lockout (UVLO) circuit, which prevents the device from turning on when the voltage at this node is less than the UVLO threshold. OUTPUT VOLTAGE All output voltages on the SMB113A/B and SMB117/A can be set via the non-volatile configuration registers. Each of the four step-down output voltages on the SMB113A/B and SMB117/A can be adjusted for 100% duty cycle or 0% duty cycle operation. When 100% duty cycle mode is selected, the output voltage can be set up to the input voltage on the device, while the minimum output voltage is limited to the min duty cycle specification in the DC operating characteristics section. When the 0% duty cycle mode is selected, the maximum duty cycle is limited to the max duty cycle specification in the DC operating characteristics section. POWER-ON/OFF CONTROL Sequencing can be initiated: automatically, by a volatile I2C Power on command, or by asserting the PWREN pin. When the PWREN pin is programmed to initiate sequencing, it can be level or edge triggered. The PWREN input has a programmable de-bounce time of 100, 50, or 25ms. The de-bounce time can also be disabled. When configured as a push-button enable, PWREN must be asserted longer than the de-bounce time before sequencing can commence, and pulled low for the same period to disable the channels. ENABLE Each output can be enabled and disable by an enable signal. The enable signal is can be provided from either the PWREN pin or by the contents of the enable register. When enabling a channel from the enable register, the register contents default state must be set so that the output will be enabled or disabled following a POR (power on reset). The default state is programmable. CASCADE SEQUENCING Each channel on the SMB113A/B and SMB117/A may be placed in any one of 4 unique sequence positions, as assigned by the configurable non-volatile register contents. The SMB113A/B and SMB117/A navigate between each sequence position using a feedbackbased cascade-sequencing circuit. Cascade sequencing is the process in which each channel is continually compared against a programmable reference voltage until the voltage on the monitored channel exceeds the reference voltage, at which point an internal sequence position counter is incremented and the next sequence position is entered. In the event that a channels enable input is not asserted when the channel is to be sequenced on, that sequence position will be skipped and the channel in the next sequence position will be enabled.
Figure 5 - Power on sequencing waveforms. Time = 4ms/devision, Scale = 1V/devision
Ch 1 = 3.3V output (Yellow trace) Ch 2 = 2.5V output (Blue trace) Ch 3 = 1.8V output (Purple trace) Ch 4 = 1.2V output (Green trace)
POWER ON/OFF DELAY There is a programmable delay between when channels in subsequent sequence positions are enabled. The delay is programmable at 50, 25, 12.5 and 1.5ms intervals. This delay is programmable for each of the four sequence positions.
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
MANUAL MODE The SMB113A/B and SMB117/A provide a manual power-on mode in which each channel may be enabled individually irrespective of the state of other channels. In this mode, the enable signal has complete control over the channel, and all sequencing is ignored. In Manual mode, channels will not be disabled in the event of a UV/OV fault on any output or the VBATT pin. FORCE-SHUTDOWN When a battery fault occurs, a UV/OV is detected on any output, or an I2C force-shutdown command is issued, all channels will be immediately disabled, ignoring sequence positions or power off delay times. SEQUENCE TERMINATION TIMER At the beginning of each sequence position, an internal programmable timer will begin to time out. When this timer has expired, the SMB113A/B and SMB117/A will automatically perform a force-shutdown operation. This timer is user programmable with a programmable sequence termination period (tPST) of 50, 100, 200 ms; this function can also be disabled. POWER OFF SEQUENCING The SMB113A/B and SMB117/A have a power-off sequencing operation. During a power off operation, the supplies will be powered off in the reverse order they where powered on in. During the power off sequencing, all enables are ignored. When a power-off command is issued the SMB113A/B and SMB117/A will set the sequence position counter to the last sequence position and disable that channel without soft-start control; once off, the power off delay for the channel(s) in the next to last sequence position will begin to timeout, after which that channel(s) will be disabled. This process will continue until all channels have been disabled and are off. The programmable If a channel fails to turn off within the sequence termination period, the sequence termination timer will initiate a force shutdown, if enabled. INPUT AND OUTPUT MONITORING Both products monitor all outputs for under-voltage (UV) and over-voltage (OV) faults. The monitored levels are user programmable, and may be set at 5, 10, 15, and 20 percent of the nominal output voltage. The VBATT pin is monitored for two user programmable UV settings. The VBATT UV settings are programmable from 2.55V to 3.45V in 150mV increments. Once the UV/OV voltage set points have been violated, the SMB113A/B and SMB117/A can be programmed to respond in one of three ways, perform: a power-off operation, a force-shutdown operation and-or it can trigger the nRESET/HEALTHY pin. SOFT START The SMB113A/B and SMB117/A provide a programmable soft-start function for all PWM outputs. The soft-start control limits the slew rate that each output is allowed to ramp up without the need for an external capacitor. The soft start slew rate is proportional to the product of the output voltage and a slew rate reference. This global reference is programmable and may be set to 400, 200, 100, 67, 50, 33, 25, and 20 Volts per second. The slew rate control can also be disabled on any channel not requiring the feature. DYNAMIC VOLTAGE MANAGEMENT The SMB113A/B/117/A have two additional voltage settings, dynamic voltage control high and low settings. Together with the nominal voltage setting, three pre-determined voltage levels can be used. The three voltage levels are ideal for situations where a core voltage needs to be reduced for power conservation. The dynamic voltage control high and low settings have the same voltage range as the controllers' nominal output voltage. These settings are stored in the non-volatile configuration registers and can be set by a write to volatile configuration registers. The dynamic voltage control command registers contain two bits for each channel that adjust the output voltages to the high, low or nominal set point after a volatile I2C write command. A seven level dynamic voltage control option is available for channel 3. When enabled, seven level dynamic voltage control allows channel 3 to be dynamically modified to one of seven pre-determined voltage levels. This transition is made by means of a volatile I2C write command. When all channels are at their voltage setting, a bit is set in the dynamic voltage control status registers.
Vout R2 R1
COMP1
VREF
+ -
Soft-Start Slew Rate=SRref* (1 + R2/R1) Vout= Vref* (1 + R2/R1)
Figure 6 - The output voltage is set by the voltage divider. The VREF voltage is programmable from 0 to 1.0 volt in 4mV increments via the I2C interface
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION
High Voltage Operation: While the SMB113A has a max input voltage of 6.0V the controller can operate to0 much higher voltages by using the circuit depicted below. By inserting a capacitor, C1, in series with the HSDRV gate signal the HSDRV pin is isolated from the 12V supply, and the AC coupling capacitor acts as a level translator transferring the 0-5V signal from the HSDRV pin to a 12V to 7V (12V-5V = 7V) signal at the gate of the PFET. When the gate stops switching the capacitor
becomes an open circuit and the gate will be pulled high by R1 turning off the output. The schottky diode and the pull-up resistor are used for DC restoration and as a pull-up respectively. Since the converter runs directly from the input supply (12V in this instance) the efficiency is consistent with that of a synchronous converter. Typical efficiency curves are shown below.
5V time C1 AC Coupling capacitor DC Restoration
12V 7V HSDRV time 0.1uF Schottky
All power comes directly from 12V supply Q2(P) +12V
Q6
R1
1K C28 22uF C33 0.1uF Q1(N) NP FDC6420C
L1 1 3.3uH C45 22uF C51 0.1uF Vout
LSDRV
Figure 7 - High-voltage operation
Summit Microelectronics, Inc
2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Figure 8 - SMB113A applications schematic.
Summit Microelectronics, Inc 2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Item
1 2 3 4 5
Description 300, 1/16W, 1%, 0603, SMD 6.04K, 1/16W, 1%, 0603, SMD 4.99K, 1/16W, 1%, 0603, SMD 6.98K, 1/16W, 1%, 0603, SMD 47, 1/16W, 1%, 0603, SMD 3, 1/16W, 1%, 0603, SMD 10K, 1/16W, 1%, 0603, SMD 300, 1/16W, 1%, 0603, SMD
Vendor / Part Number Vishay CRCW06033000F Vishay CRCW06036041F Vishay CRCW06034991F Vishay CRCW06036981F Vishay CRCW06034702F Vishay CRCW06033R01F Vishay CRCW06031002F Vishay CRCW06031000F
Qty Ref. Des. 4 1 2 1 5 8 1 4 R1, R4, R6, R8 R2 R3, R5 R7 R9, R18, R19, R20, R21 R10, R11, R12, R13, R14, R15, R16, R17 R20 R22, R23, R24, R27 C1, C3, C6, C8, C16, C21, C26, C28, C31, C33, C34, C36, C38, C40, C42 C2, C35 C4, C25, C27, C29, C37 C5, C7, C15, C20, C9 C10, C18 C11, C22 C13 C17, C12 C14, C19 C23 C24 Q1-Q4 U1
Resistors
6 7 8
Capacitors
9 10 11 12 13 14
0.1uF, 16V, ceramic, X7R, 0603, SMD
Kemet C0603C104K4RACTU Panasonic ECJ-1VF1A105Z Kemet C0805C106K9PACTU TDK C3225X7R1E106M Murata GRM1885C2A331JA01D Vishay VJ0603A121KXAA Murata GRM188R72A681KA01D Panasonic ECJ-1VC1H470J Kemet C0603C471K5RACTU Murata GRM1885C2A331JA01D Murata GRM188R72A221KA01D Vishay VJ0603A102KXAA Fairchild, FDC6420C Summit Microelectronics Sumida CDR7D28MNNP6R8NC
15 2 9 4 1 2 2 1 2 2 1 1 4 1
1uF, 10V, ceramic, Y5V, 0603, SMD 10uF, 6.3V, ceramic, X5R, 0805, SMD 10uF, 25V, ceramic, X7R, 1210, SMD 330pF, 50V, ceramic, C0G, 0603, SMD 120pF, 50V, ceramic, C0G, 0603, SMD 680pF, 100V, ceramic, X7R, 0603, SMD
15 16 17 18 19 20 21 22
47pF, 50V, ceramic, NP0, 0603, SMD 470pF, 50V, ceramic, X7R, 0603, SMD 820pF, 50V, ceramic, C0G, 0603, SMD 220pF, 50V, ceramic, C0G, 0603, SMD 1000pF, 50V, ceramic, C0G, 0603, SMD
Semiconductors
MOSFET, Complementary SMB113ANC
Magnetics
Inductor, 6.8uH, 2.75A, SMD, Shielded
4
L1-4
Summit Microelectronics, Inc
2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
D1 Schottky VIN
Q2(P) C12 0.1uF R4 1K C16 22uF C17 0.1uF Q5 FDC6420C L1 Q1(N) D8 VBATT R9 49.9K HEALTHY/nRESET HOST_RESET PWREN0 1 1 1 Optional Push-Button Enable 2 11 26 1 3.3uH C5 22uF U1 SMB113A HSDRV_CH0 LSDRV_CH0 COMP1_CH0 COMP2_CH0 VM_CH0 HVSUP0 HSDRV_CH1 LSDRV_CH1 COMP1_CH1 COMP2_CH1 VM_CH1 HVSUP1 HSDRV_CH2 LSDRV_CH2 COMP1_CH2 COMP2_CH2 VM_CH2 HVSUP2 HSDRV_CH3 LSDRV_CH3 COMP1_CH3 COMP2_CH3 VM_CH3 HVSUP3 1 31 3 4 5 32 10 8 12 13 14 9 19 17 21 20 22 18 25 23 28 27 29 24 C9 22pF R2 499 R1 4.99K C10 Q2(P) D3 Schottky VIN C18 0.1uF Q4 FDC6420C R12 1K C20 22uF C22 0.1uF Q1(N) D9 R13 0 C37 22pF R23 499 R22 4.99K C38 3300pF R14 100 L2 3.3uH C34 22uF 3300pF R3 100 C8 330pF C7 0.1uF CH0
R5 0
HEALTHY HOST_RESET PWREN0
+12V VIN 1 SW1 R10 1K Q1 NPN D7 5.6V
SDA SCL
6 7
SDA SCL
C25 0.1uF
1 C36 330pF C35
CH1
0.1uF
VBATT 16 15 1 VBATT VDDCAP GND 30
VBATT
C15 1uF
C14
C2
C1 0.1uF
VBATT 0.1uF 1uF D5 Schottky VIN C24 C11 0.1uF R16 1K C27 22uF C13 0.1uF D2 VBATT R17 0 C29 0.1uF 0.1uF Q3
Q2(P)
Optional For Programming SMB113A
DongleVCC
L3 Q1(N) NP FDC6420C D10 3.3uH C40 C43 22pF C42 330pF 22uF C41 0.1uF
1
CH2
R7 47K
R30 47K
J1 10 8 6 4 2 Rsrv10 +5V Rsrv8 +10V MR Rsrv5 SDA Gnd3 SCL Gnd I2C 9 7 5 3 1
DongleVCC
SDA SCL
R25 499 C19 0.1uF R24 4.99K C44 3300pF R37 100
C21 0.1uF D6 Schottky C30 0.1uF VIN
Q2
Q2(P)
R19 1K C31 22uF
C32 0.1uF
L4 Q1(N) FDC6420C D11 3.3uH 1 C46 C47 0.1uF C48 330pF C49 22pF R29 499 R28 4.99K C50 3300pF R39 100 CH3
R20 0
22uF
Figure 9 - Applications schematic showing SMB113A operation from a +12V input supply.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Item
Description-
Vendor / Part Number
Qty
Ref. Des. C1, C3, C7, C11, C13, C12, C14, C17, C18, C19, C21, C22, C24, C25, C29, C30, C32, C35, C41, C47 C2, C15 C5, C16, C20, C27, C31, C34, C40, C46 C8, C36, C42, C48 C9, C37, C43, C49 C10, C38, C44, C50
Capacitors 1 2 3 4 5 6 0.1uF, 50V, ceramic, X7R, 0603, SMD 1uF, 25V, ceramic, X5R, 0805, SMD Murata GRM188R71H104KA93D 19 2 9 4 4 2
Murata GRM216R61E105KA12 Murata 22uF, 16V, ceramic, X5R, 1210, SMD GRM32ER61C226ME20L 330pF, 50V, ceramic, NP0, 0603, SMD Panasonic ECJ-1VC1H331J Murata 22pF, 50V, ceramic, NP0, 0603, SMD GRM1885C1H470JA01D Murata 3300pF, 100V, ceramic, X7R, 0603, SMD GRM188R71H332KA01D Resistors 499, 1/10W, 1%, 0603, SMD 100, 1/10W, 1%, 0603, SMD 1K, 1/10W, 1%, 0603, SMD 0, 1/10W, 1%, 0603, SMD 49.9K, 1/10W, 1%, 0603, SMD 2K, 1/10W, 1%, 0603, SMD 4.99K, 1/10W, 1%, 0603, SMD Semiconductors Diode Schottky, 20V, 200mA, SS-mini Diode, Schottky, 40V, 500mA SOD-123 LED, Red, 0805, SMD Zener Diode, 5.6V, 500mW, SOD-123 NPN, 40V, 1A, SOT-89 SMB113A Magnetics Inductor 3.3uH Vishay CRCW06034990F Vishay CRCW06031000F Vishay CRCW06031001F Vishay CRCW06030R00F Vishay CRCW06034992F Vishay CRCW06032001F Vishay CRCW06034991F Panasonic MA2SD2400L Diodes Inc. B0540W-7 Lumex SML-LXT0805SRWTR ON Semi MMSZ5V6T1G Zetex FCX491A Summit Microelectronics TDK HCP0703-3R3-R
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
4 4 5 4 4 1 4 4 5 2 1 1 4 1 4
R2, R23, R25, R29 R3, R14, R37, R39 R4, R10, R12, R16, R19 R5, R13, R17, R20 R6, R7, R8, R30 R9 R1, R22, R24, R28 D1, D3, D5, D6 D2, D12, D13, D14, D15 D4 D7 Q1 Q2, Q3, Q4, Q5 U1 L1, L2, L3, L4
MOSFET, Complementary, 20V, SSOT-6 Analog Power AM3520C
Summit Microelectronics, Inc
2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Q12 4 R11 0 VBATT 1 2 3 C16 22uF C17 0.1uF FDS6675BZ Q13 4 R5 0 5 6 7 8 1 2 3 U1 R9 2K SMB117 HSDRV_CH0 LSDRV_CH0 COMP1_CH0 COMP2_CH0 VM_CH0 HVSUP0 HSDRV_CH1 LSDRV_CH1 COMP1_CH1 COMP2_CH1 VM_CH1 HVSUP1 HSDRV_CH2 LSDRV_CH2 COMP1_CH2 COMP2_CH2 VM_CH2 HVSUP2 HSDRV_CH3 LSDRV_CH3 COMP1_CH3 COMP2_CH3 VM_CH3 HVSUP3 1 31 3 4 5 32 10 8 12 13 14 9 R15 0 19 17 21 20 22 18 25 23 28 27 29 24 VBATT 1 2 3 FDS6675BZ Q11 4 R13 0 5 6 7 8 1 2 3 FDS6680AS C37 C11 0.1uF 22pF R23 499 R22 10K C38 3300pF R14 100 DongleVCC C13 0.1uF R7 47K R30 47K 10 8 6 4 2 J1 Rsrv10 +5V Rsrv8 +10V MR Rsrv5 SDA Gnd3 SCL Gnd I2C 9 7 5 3 1 DongleVCC D2 VBATT R18 0 C19 0.1uF C27 22uF C21 0.1uF C29 0.1uF 4 R17 0 VBATT 4 1 2 3 FDS6675BZ Q7 5 6 7 8 1 2 3 FDS6680AS C43 22pF R25 499 R24 10K C44 3300pF R37 100 Q6 5 6 7 8 FDS6680AS C9 22pF R2 499 R1 10K C10 3300pF R3 100 L1 1 2.0uH C5 22uF C8 330pF C7 0.1uF CH0 5 6 7 8
D8
VBATT
HEALTHY/nRESET HOST_RESET PWREN0
1 1 1 Optional Push-Button Enable
2 11 26
HEALTHY HOST_RESET PWREN0
Q10 4 5 6 7 8
SW1
SDA SCL
6 7
SDA SCL
D9
C20 22uF
C22 0.1uF
TP15 VBATT 1
VBATT 16 15 VBATT VDDCAP GND
L2 1 2.0uH C34 22uF C35 0.1uF CH1
C15 1uF
C14
C2
C1 0.1uF
30
VBATT
0.1uF 1uF
C36 330pF
Optional For Programming SMB113A
D10
SDA SCL
L3 1 2.0uH C40 22uF C42 330pF C41 0.1uF CH2
Q8 4 R21 0 VBATT 1 2 3 C31 22uF C32 0.1uF FDS6675BZ Q9 4 R20 0 5 6 7 8 1 2 3 FDS6680AS C49 22pF C48 330pF 5 6 7 8
D11
L4 1 2.0uH C46 22uF C47 0.1uF
CH3
R29 499 R28 10K C50 3300pF R39 100
Figure 10 - Applications schematic showing SMB117 operation from a +5V input supply with 10A output current capability.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Item Capacitors 1 2 3 4 5 6 0.1uF, 50V, ceramic, X7R, 0603, SMD 1uF, 25V, ceramic, X5R, 0805, SMD Murata GRM188R71H104KA93D 19 2 9 4 4 2 C1, C3, C7, C11, C13, C12, C14, C17, C18, C19, C21, C22, C24, C25, C29, C30, C32, C35, C41, C47 C2, C15 C5, C16, C20, C27, C31, C34, C40, C46 C8, C36, C42, C48 C9, C37, C43, C49 C10, C38, C44, C50 DescriptionVendor / Part Number Qty Ref. Des.
Murata GRM216R61E105KA12 Murata 22uF, 16V, ceramic, X5R, 1210, SMD GRM32ER61C226ME20L 330pF, 50V, ceramic, NP0, 0603, SMD Panasonic ECJ-1VC1H331J Murata 22pF, 50V, ceramic, NP0, 0603, SMD GRM1885C1H470JA01D Murata 3300pF, 100V, ceramic, X7R, 0603, SMD GRM188R71H332KA01D
Resistors
7 8 9 10 11 12
13
499, 1/10W, 1%, 0603, SMD 100, 1/10W, 1%, 0603, SMD 1K, 1/10W, 1%, 0603, SMD 0, 1/10W, 1%, 0603, SMD 49.9K, 1/10W, 1%, 0603, SMD 2K, 1/10W, 1%, 0603, SMD 10K, 1/10W, 1%, 0603, SMD
Vishay CRCW06034990F Vishay CRCW06031000F Vishay CRCW06031001F Vishay CRCW06030R00F Vishay CRCW06034992F Vishay CRCW06032001F Vishay CRCW06031002F Diodes Inc. B0540W-7 Lumex SML-LXT0805SRWTR Fairchild FDS6680AS Fairchild FDS6675BZ Summit Microelectronics
4 4 5 4 4 1 4 5 2
R2, R23, R25, R29 R3, R14, R37, R39 R4, R10, R12, R16, R19 R5, R13, R17, R20 R6, R7, R8, R30 R9 R1, R22, R24, R28 D2, D12, D13, D14, D15 D4 Q7, Q9, Q11, Q13
Semiconductors
14 15 16 17 18 19 Diode, Schottky, 40V, 500mA SOD-123 LED, Red, 0805, SMD MOSFET, NFET, 20V, SOT-8 MOSFET, PFET, 20V, SOT-8 SMB117 Magnetics Inductor 2.0uH Wurth 744314200 4 L1, L2, L3, L4
4 1
Q6, Q8, Q10, Q12 U1
Summit Microelectronics, Inc
2111 2.4 6/24/2008
24
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
COMPONENT SELECTION Buck Outputs: Inductor: The starting point design of any and DC/DC converter is the selection of the appropriate inductor for the application. The optimal inductor value will set the inductor current at 30% of the maximum expected load current. The inductors current for a Buck converter is as follows: Buck: Equation 1: possible in order to minimize trace inductance that would otherwise limit the rate of change of the current. Output capacitor Each converter should have a high value low impedance output capacitor to act as a current reservoir for current transients and to. This capacitor should be either a X5R or X7R MLCC. For a Buck converter, the value of this capacitance is determined by the maximum expected transient current. Since the converter has a finite response time, during a load transient the current is provided by the output capacitor. Since the voltage across the capacitor drops proportionally to the capacitance, a higher output capacitor reduces the voltage drop until the feedback loop can react to increase the voltage to equilibrium. The voltage drop can be calculated according to: Equation 2:
L=
Vo(V IN - Vo) Vin * 0.3 * I MAX * f
Where Vo is the output voltage, VIN is the input voltage, f is the frequency, and IMAX is the max load current. For example: For a 1.2V output and a 3.6V input with a 500mA max load, and a 1MHz switching frequency the optimal inductor value is:
V=
I *T C
L=
1.2(3.6 - 1.2) = 5.3uH 3.6 * 0.3 * 0.5 * 1E 6
Choosing the nearest standard inductor value we select a 5.6uH inductor. It is important that the inductor has a saturation current level greater than 1.2 times the max load current. Other parameters of interest when selecting an inductor are the DCR (DC winding resistance). This has a direct impact on the efficiency of the converter. In general, the smaller the size of the inductor is the larger the resistance. As the DCR goes up the power loss increases according to the I2R relation. As a result choosing a correct inductor is often a trade off between size and efficiency. Input Capacitor Each converter should have a high value low impedance input (or bulk) capacitor to act as a current reservoir for the converter stage. This capacitor should be either a X5R or X7R MLCC (multi-layer-ceramic capacitor). The value of this capacitor is normally chosen to reflect the ratio of the input and output voltage with respect to the output capacitor. Typical values range from 2.2uF to 10uF. For Buck converters, the input capacitor supplies square wave current to the inductor and thus it is critical to place this capacitor as close to the PFET as
Where I is the load or transient current, T is the time the output capacitor is supporting the output and C is the output capacitance. Typical values range from 10uF to 44uF. Other important capacitor parameters include the Equivalent Series Resistance (E.S.R) of the capacitor. The ESR in conjunction with the ripple current determines the ripple voltage on the output, for typical values of MLCC the ESR ranges from 2-10m. In addition, carful attention must be paid to the voltage rating of the capacitor the voltage rating of a capacitor must never be exceeded. In addition, the DC bias voltage rating can reduce the measured capacitance by as much as 50% when the voltage is at half of the max rating, make sure to look at the DC bias de-rating curves when selecting a capacitor. MOSFETS When selecting the appropriate FET to use attention must be paid to the gate to source rating, input capacitance, and maximum power dissipation. Most FETs are specified by an on resistance (RDSON) for a given gate to source voltage (VGS). It is essential to ensure that the FETs used will always have a VGS voltage grater then the minimum value shown on the datasheet. It is worth noting that the specified VGS voltage must not be confused with the threshold voltage of the FET.
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
The input capacitance must be chosen such that the rise and fall times specified in the datasheet do not exceed ~5% of the switching period. To ensure the maximum load current will not exceed the power rating of the FET, the power dissipation of each FET must be determined. It is important to look at each FET individually and then add the power dissipation of complementary FETs after the power dissipation over one cycle has been determined. The Power dissipation can be approximated as follows: Equation 3: Equations 4, 5:
Buck - NFET : (1 - Buck - PFET :
VO ) *T VIN
VO *T VIN
P ~ R DSON * I L * TON
2
Where TON is the on time of the primary switch. TON can be calculated as follows:
Compensation: Summit provides a design tool to called Summit Power Designer" that will automatically calculate the compensation values for a design or allow the system to be customized for a particular application. The power designer software can be found at http://www.summitmicro.com/prod_select/xls/SummitP owerDesigner_Install.zip.
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SMB113A/B/SMB117/A
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
The end user can obtain the Summit SMX3200 parallel port programming system or the I2C2USB (SMX3201) USB programming system for device prototype development. The SMX3200(1) system consist of a programming Dongle, cable and WindowsTM GUI software. It can be ordered on the website or from a local representative. The latest revisions of all software and an application brief describing the SMX3200 and SMX3201 are available from the website (http://www.summitmicro.com). The SMX3200 programming Dongle/cable interfaces directly between a PC's parallel port and the target application; while the SMX3201 interfaces directly to the PC's USB port and the target application. The device is then configured on-screen via an intuitive graphical user interface employing drop-down menus. The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMB113A/B or SMB117/A via the programming Dongle and cable. An example of the connection interface is shown in Figure 11. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application.
Top view of straight 0.1" x 0.1 closed-side connector. SMX3200/SMX3201 interface cable connector. Pin 9, 5.0V Pin 10, Reserved Pin 8, Reserved Pin 7, 10V Pin 5, Reserved Pin 6, MR# Pin 4, SDA Pin 3, GND Pin 2, SCL Pin 1, GND
VBATT
SMB113A/B SMB117/A
SDA SCL
10 8 6 4 2
9 7 5 3 1
0.1F
GND
Figure 11 - SMX3200/SMX3201 Programmer I2C serial bus connections to program the SMB113A/B or SMB117/A.
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE Access to the configuration registers, general-purpose memory and command and status registers is carried out over an industry standard 2-wire serial interface (I2C). SDA is a bi-directional data line and SCL is a clock input. Data is clocked in on the rising edge of SCL and clocked out on the falling edge of SCL. All data transfers begin with the MSB. During data transfers, SDA must remain stable while SCL is high. Data is transferred in 8-bit packets with an intervening clock period in which an Acknowledge is provided by the device receiving data. The SCL high period (tHIGH) is used for generating Start and Stop conditions that precede and end most transactions on the serial bus. A high-to-low transition of SDA while SCL is high is considered a Start condition while a low-to-high transition of SDA while SCL is high is considered a Stop condition. The interface protocol allows operation of multiple devices and types of devices on a single bus through unique device addressing. The address byte is comprised of a 7-bit device type identifier (slave address). The remaining bit indicates either a read or a write operation. Refer to Table 1 for a description of the address bytes used by the SMB113A/B. The device type identifier for the memory array, the configuration registers and the command and status registers are accessible with the same slave address. The slave address can be can be programmed to any seven bit number 0000000BIN through 1111111BIN. WRITE Writing to the memory or a configuration register is illustrated in Figures 12and 13 A Start condition followed by the slave address byte is provided by the host; the SMB113A/B and SMB117/A respond with an Acknowledge; the host then responds by sending the memory address pointer or configuration register address pointer; the SMB113A/B and SMB117/A respond with an acknowledge; the host then clocks in one byte of data. For memory and configuration register writes, up to 15 additional bytes of data can be clocked in by the host to write to consecutive addresses within the same page. After the last byte is clocked in and the host receives an Acknowledge, a Stop condition must be issued to initiate the nonvolatile write operation. READ The address pointer for the non-volatile configuration registers and memory registers as well as the volatile command and status registers must be set before data can be read from the SMB113A/B or the SMB117/A. This is accomplished by issuing a dummy write command, which is a write command that is not followed by a Stop condition. A dummy write command sets the address from which data is read. After the dummy write command is issued, a Start command followed by the address byte is sent from the host. The host then waits for an Acknowledge and then begins clocking data out of the slave device. The first byte read is data from the address pointer set during the dummy write command. Additional bytes can be clocked out of consecutive addresses with the host providing an Acknowledge after each byte. After the data is read from the desired registers, the read operation is terminated by the host holding SDA high during the Acknowledge clock cycle and then issuing a Stop condition. Refer to Figure 14for an illustration of the read sequence. CONFIGURATION REGISTERS The configuration registers are grouped with the general-purpose memory. GENERAL-PURPOSE MEMORY The 96-byte general-purpose memory block is segmented into two continuous independently lockable blocks. The first 48-byte memory block begins at register address pointer A0HEX and the second memory block begins at the register address pointer C0HEX; see Table 1. Each memory block can be locked individually by writing to a dedicated register in the configuration memory space.
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
GRAPHICAL USER INTERFACE (GUI) Device configuration utilizing the Windows based SMB113A/B/117/A graphical user interface (GUI) is highly recommended. The software is available from the Summit website (http://www.summitmicro.com ). Using the GUI in conjunction with this datasheet, simplifies the process of device prototyping and the Slave Address 0000000BIN to 1111111BIN Register Type Configuration Registers are located in 00 HEX thru 9FHEX General-Purpose Memory Block 0 is located in A0 HEX thru BFHEX General-Purpose Memory Block 1 is located in C0 HEX thru FFHEX interaction of the various functional blocks. A programming Dongle (SMX3200) is available from Summit to communicate with the SMB113A/B and SMB117/A. The Dongle connects directly to the parallel port of a PC and programs the device through a cable using the I2C bus protocol. See figure 11 and the SMX3200 Data Sheet.
Table 1 - Possible address bytes used by the SMB113A/B and the SMB117/A.
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster S T A R T S A 3 Slave S A 2 S A 1 S A 0 Bus Address A 2 A 1 A 0 C 7 A C K C 6 Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5 Data D 4 D 3 D 2 D 1 D 0 A C K S T O P
W
Figure 12 - Register Byte Write
S T A R T S A 3 Slave S A 2 S A 1 S A 0
M aster
Bus Address A 2 A 1 A 0 C 7 A C K C 6
Configuration Register Address C 5 C 4 C 3 C 2 C 1 C 0 A C K D 7 D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0 A C K
W
M aster D 7 Slave D 6 D 5
Data (2) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5
Data (16) D 4 D 3 D 2 D 1 D 0 A C K
S T O P
Figure 13 - Register Page Write
S T A R T S A 3 Slave S A 2 S A 1 S A 0 S T A R T C 1 C 0 A C K S A 3 S A 2 S A 1 S A 0
Master
Bus Address A 2 A 1 A 0 C 7 A C K C 6
Configuration Register Address W C 5 C 4 C 3 C 2
Bus Address A 2 A 1 A 0
R A C K
Master D 7 Slave D 6 D 5
Data (1) D 4 D 3 D 2 D 1 D 0 A C K D 7 D 6 D 5 D 2 D 1 D 0 A C K D 7 D 6 D 5
Data (n) D 4 D 3 D 2 D 1 D 0
N A C K
S T O P
Figure 14 - Register Read
Summit Microelectronics, Inc
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SMB113A/B/SMB117/A
Preliminary Information
PACKAGE
Summit Microelectronics, Inc
2111 2.4 6/24/2008
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SMB113A/B/SMB117/A
Preliminary Information
PART MARKING
SUMMIT SMB113AN xx
Summit Part Number: SMB113A, SMB113B, SMB117 or SMB117A Status Tracking Code (01, 02,...) (Summit Use)
Annn L AYYWW
Pin 1
Date Code (YYWW) Lot tracking code (Summit use) 100% Sn, RoHS compliant
Drawing not to scale
Part Number suffix (Contains Customer specific ordering requirements) Product Tracking Code (Summit use)
ORDERING INFORMATION
Summit Part Number Package SMB113A N C nnn L Environmental Attribute L = 100% Sn, RoHS compliant Part Number Suffix Temperature Range
C = Commercial BLANK = Industrial
The default device ordering number is SMB113ANC-650L. It is tested over the commercial temperature range. The ordering number is derived from the customer supplied hex file. New device suffix numbers are assigned to non-default requirements.
SMB113A, SMB113B, SMB117 or SMB117A N = 32-Pad QFN
Specific requirements are contained in the suffix
NOTICE
NOTE 1 - This is a Preliminary data sheet that describes a Summit that is in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user's specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 2.4 This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at http://www.summitmicro.com for data sheet updates. (c) Copyright 2007 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER FOR A GREEN PLANETTM ADOCTM is a registered trademark of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation.
Summit Microelectronics, Inc
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